A goal of integrated circuit (IC) testing is to distinguish defect-free devices from those that have defects. Many commonly occurring defects, however, are difficult to detect and characterize during traditional testing. In particular, there are a number of defects that are difficult to test during voltage-based testing, static leakage current (“IDDQ”) testing, and stress-related testing.
Relative to voltage-based testing, testing under nominal well-bias conditions does not always detect defects. For instance, voltage-based testing at nominal well-bias conditions may be completed using a low-Vdd test to aid in detection of defects. However, not all defects are readily apparent using such tests.
Relative to IDDQ testing, increased background currents make it difficult to distinguish between defect-related IDDQ, i.e., those usually manifested in an elevated IDDQ, from normal defect-free chip background current. One proposed solution to this problem is to uniformly modify the well and/or substrate biases so that the threshold voltages of all of the transistors are increased in order to decrease leakage current and make defect-related IDDQ discernable. However, this solution overlooks the relationships between IDDQ and substrate bias that may be leveraged to detect defects. Another proposed solution is IDDQ versus Vdd characterization. Unfortunately, defects are still difficult to discern and characterize based on this comparison.
Relative to stress-related testing, latent defects may exist in manufactured ICs that are initially benign and therefore not detectable at wafer or package level test. However, degradation during use can cause the circuit to fail before the end of its specified life. Accelerated life stress tests are used to detect such defect-related “reliability fails” so that defect-laden ICs are not shipped to the customer. Today, elevated voltage stress tests and elevated temperature/voltage burn-in tests are used as accelerated life stresses. One of the reasons for burning in chips at high voltage and temperature, or voltage stressing chips at high voltage, is to create large currents. Such currents are especially useful for opening up resistive-open-type defects. Another reason for generating high currents is to increase power dissipation, which generates heat and, in turn, mechanical stresses. These mechanical stresses are also especially useful for opening up resistive-open-type defects. Unfortunately, both types of tests are becoming increasingly difficult to apply. First, voltage stress is problematic relative to near-future technologies because placing a large electric field across the gate oxide has increasingly forced the chips into gate oxide failure prematurely. Second, burn-in is also becoming less desirable as power, especially static power, exceeds equipment delivery capabilities. Also, both traditional stress methods disadvantageously require compromises in design to ensure circuit functionality under the applied stresses.
In view of the foregoing, there is a need for IC testing methods that provide higher resolution voltage-based and IDDQ testing and more efficient, less damaging stress testing.